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<h1 id="firstHeading" class="firstHeading mw-first-heading"><span class="mw-page-title-main">Bfloat16</span></h1>

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<p><b>bfloat16</b> <i>(<span lang="en">brain floating point with 16 bits</span>)</i> ist die Bezeichnung für ein <a href="Gleitkommazahl" title="Gleitkommazahl">Gleitkommaformat</a> in Computersystemen. Es handelt sich um ein <a href="Dualsystem" title="Dualsystem">binäres</a> Datenformat mit einem Bit für das <a href="Vorzeichen_(Zahl)" title="Vorzeichen (Zahl)">Vorzeichen</a>, 8 Bits für den <a href="Potenz_(Mathematik)" title="Potenz (Mathematik)">Exponenten</a> und 7 Bits für die <a href="Mantisse" title="Mantisse">Mantisse</a>. Es handelt sich also um eine in der Mantisse gekürzte Version des halbgenauen <a href="IEEE_754" title="IEEE 754">IEEE 754</a> <a href="Minifloat" title="Minifloat">Datentyps</a>.

</p><p><i>bfloat16</i> wird insbesondere in Systemen für maschinelles Lernen eingesetzt, wie beispielsweise <a href="TensorFlow_Processing_Unit" class="mw-redirect" title="TensorFlow Processing Unit">TPUs</a><sup id="cite_ref-clou_Avai_1-0" class="reference"><a href="#cite_note-clou_Avai-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-blog_Comp_2-0" class="reference"><a href="#cite_note-blog_Comp-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-gith_tens_3-0" class="reference"><a href="#cite_note-gith_tens-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup>, sowie bestimmten <a href="Intel_Xeon" title="Intel Xeon">Intel-Xeon</a>-Prozessoren und Intel FPGAs.<sup id="cite_ref-vent_Intel_4-0" class="reference"><a href="#cite_note-vent_Intel-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-top5_Intel_5-0" class="reference"><a href="#cite_note-top5_Intel-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-toms_Intel_6-0" class="reference"><a href="#cite_note-toms_Intel-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup>

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<div class="mw-heading mw-heading2"><h2 id="Quellen">Quellen</h2></div>

<li id="cite_note-clou_Avai-1"><span class="mw-cite-backlink"><a href="#cite_ref-clou_Avai_1-0">↑</a></span> <span class="reference-text"><span class="cite"><a rel="nofollow" class="external text" href="https://cloud.google.com/tpu/docs/tensorflow-ops"><i>Available TensorFlow Ops | Cloud TPU | Google Cloud.</i></a> In: <i>Google Cloud.</i><span class="Abrufdatum"> Abgerufen am 23. Mai 2018</span> (englisch): „This page lists the TensorFlow Python APIs and graph operators available on Cloud TPU.“</span><span style="display: none;" class="Z3988" title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Adc&rfr_id=info%3Asid%2Fde.wikipedia.org%3ABfloat16&rft.title=Available+TensorFlow+Ops+%26%23124%3B+Cloud+TPU+%26%23124%3B+Google+Cloud&rft.description=Available+TensorFlow+Ops+%26%23124%3B+Cloud+TPU+%26%23124%3B+Google+Cloud&rft.identifier=&rft.date=&rft.language=en"> </span></span>

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<li id="cite_note-blog_Comp-2"><span class="mw-cite-backlink"><a href="#cite_ref-blog_Comp_2-0">↑</a></span> <span class="reference-text"><span class="cite">Elmar Haußmann: <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180426200043/https://blog.riseml.com/comparing-google-tpuv2-against-nvidia-v100-on-resnet-50-c2bbb6a51e5e"><i>Comparing Google’s TPUv2 against Nvidia’s V100 on ResNet-50.</i></a> In: <i>RiseML Blog.</i> 26. April 2018, archiviert vom <style data-mw-deduplicate="TemplateStyles:r250917974">

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</style><span class="dewiki-iconexternal"><a class="external text" href="https://redirecter.toolforge.org/?url=https%3A%2F%2Fblog.riseml.com%2Fcomparing-google-tpuv2-against-nvidia-v100-on-resnet-50-c2bbb6a51e5e">Original</a></span> am <span style="white-space:nowrap;">26. April 2018</span><span>;</span><span class="Abrufdatum"> abgerufen am 23. Mai 2018</span> (englisch): „For the Cloud TPU, Google recommended we use the bfloat16 implementation from the official TPU repository with TensorFlow 1.7.0. Both the TPU and GPU implementations make use of mixed-precision computation on the respective architecture and store most tensors with half-precision.“</span><span style="display: none;" class="Z3988" title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Adc&rfr_id=info%3Asid%2Fde.wikipedia.org%3ABfloat16&rft.title=Comparing+Google%E2%80%99s+TPUv2+against+Nvidia%E2%80%99s+V100+on+ResNet-50&rft.description=Comparing+Google%E2%80%99s+TPUv2+against+Nvidia%E2%80%99s+V100+on+ResNet-50&rft.identifier=https%3A%2F%2Fweb.archive.org%2Fweb%2F20180426200043%2Fhttps%3A%2F%2Fblog.riseml.com%2Fcomparing-google-tpuv2-against-nvidia-v100-on-resnet-50-c2bbb6a51e5e&rft.creator=Elmar+Hau%C3%9Fmann&rft.date=2018-04-26&rft.source=https://blog.riseml.com/comparing-google-tpuv2-against-nvidia-v100-on-resnet-50-c2bbb6a51e5e&rft.language=en"> </span></span>

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<li id="cite_note-gith_tens-3"><span class="mw-cite-backlink"><a href="#cite_ref-gith_tens_3-0">↑</a></span> <span class="reference-text"><span class="cite">Tensorflow Authors: <i>ResNet-50 using BFloat16 on TPU.</i> In: <i>Google.</i> 28. Februar 2018, ehemals im <span class="dewiki-iconexternal"><a class="external text" href="https://redirecter.toolforge.org/?url=https%3A%2F%2Fgithub.com%2Ftensorflow%2Ftpu%2Ftree%2Fmaster%2Fmodels%2Fexperimental%2Fresnet_bfloat16">Original</a></span> (nicht mehr online verfügbar)<span>;</span><span class="Abrufdatum"> abgerufen am 23. Mai 2018</span> (englisch).<span style="display:none"><a rel="nofollow" class="external text" href="http://deadurl.invalid/https://github.com/tensorflow/tpu/tree/master/models/experimental/resnet_bfloat16">@1</a></span><span style="display:none"><a rel="nofollow" class="external text" href="https://github.com/tensorflow/tpu/tree/master/models/experimental/resnet_bfloat16">@2</a></span><span style="display:none">Vorlage:Toter Link/github.com</span> <small>(Seite nicht mehr abrufbar. <a rel="nofollow" class="external text" href="http://timetravel.mementoweb.org/list/2010/https://github.com/tensorflow/tpu/tree/master/models/experimental/resnet_bfloat16">Suche in Webarchiven</a>)</small></span><span style="display: none;" class="Z3988" title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Adc&rfr_id=info%3Asid%2Fde.wikipedia.org%3ABfloat16&rft.title=ResNet-50+using+BFloat16+on+TPU&rft.description=ResNet-50+using+BFloat16+on+TPU&rft.identifier=&rft.creator=Tensorflow+Authors&rft.date=2018-02-28&rft.language=en"> </span></span>

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<li id="cite_note-vent_Intel-4"><span class="mw-cite-backlink"><a href="#cite_ref-vent_Intel_4-0">↑</a></span> <span class="reference-text"><span class="cite">Khari Johnson: <a rel="nofollow" class="external text" href="https://venturebeat.com/2018/05/23/intel-unveils-nervana-neural-net-l-1000-for-accelerated-ai-training/"><i>Intel unveils Nervana Neural Net L-1000 for accelerated AI training.</i></a> In: <i>VentureBeat.</i> 23. Mai 2018,<span class="Abrufdatum"> abgerufen am 23. Mai 2018</span> (englisch): „...Intel will be extending bfloat16 support across our AI product lines, including Intel Xeon processors and Intel FPGAs.“</span><span style="display: none;" class="Z3988" title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Adc&rfr_id=info%3Asid%2Fde.wikipedia.org%3ABfloat16&rft.title=Intel+unveils+Nervana+Neural+Net+L-1000+for+accelerated+AI+training&rft.description=Intel+unveils+Nervana+Neural+Net+L-1000+for+accelerated+AI+training&rft.identifier=&rft.creator=Khari+Johnson&rft.date=2018-05-23&rft.language=en"> </span></span>

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<li id="cite_note-top5_Intel-5"><span class="mw-cite-backlink"><a href="#cite_ref-top5_Intel_5-0">↑</a></span> <span class="reference-text"><span class="cite">Michael Feldman: <a rel="nofollow" class="external text" href="https://www.top500.org/news/intel-lays-out-new-roadmap-for-ai-portfolio/"><i>Intel Lays Out New Roadmap for AI Portfolio.</i></a> In: <i>TOP500 Supercomputer Sites.</i> 23. Mai 2018,<span class="Abrufdatum"> abgerufen am 23. Mai 2018</span> (englisch): „Intel plans to support this format across all their AI products, including the Xeon and FPGA lines“</span><span style="display: none;" class="Z3988" title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Adc&rfr_id=info%3Asid%2Fde.wikipedia.org%3ABfloat16&rft.title=Intel+Lays+Out+New+Roadmap+for+AI+Portfolio&rft.description=Intel+Lays+Out+New+Roadmap+for+AI+Portfolio&rft.identifier=&rft.creator=Michael+Feldman&rft.date=2018-05-23&rft.language=en"> </span></span>

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<li id="cite_note-toms_Intel-6"><span class="mw-cite-backlink"><a href="#cite_ref-toms_Intel_6-0">↑</a></span> <span class="reference-text"><span class="cite">Lucian Armasu: <a rel="nofollow" class="external text" href="https://www.tomshardware.com/news/intel-neural-network-processor-lake-crest,37105.html"><i>Intel To Launch Spring Crest, Its First Neural Network Processor, In 2019.</i></a> In: <i>Tom’s Hardware.</i> 23. Mai 2018,<span class="Abrufdatum"> abgerufen am 23. Mai 2018</span> (englisch): „Intel said that the NNP-L1000 would also support bfloat16, a numerical format that’s being adopted by all the ML industry players for neural networks. The company will also support bfloat16 in its FPGAs, Xeons, and other ML products. The Nervana NNP-L1000 is scheduled for release in 2019.“</span><span style="display: none;" class="Z3988" title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Adc&rfr_id=info%3Asid%2Fde.wikipedia.org%3ABfloat16&rft.title=Intel+To+Launch+Spring+Crest%2C+Its+First+Neural+Network+Processor%2C+In+2019&rft.description=Intel+To+Launch+Spring+Crest%2C+Its+First+Neural+Network+Processor%2C+In+2019&rft.identifier=&rft.creator=Lucian+Armasu&rft.date=2018-05-23&rft.language=en"> </span></span>

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